1. Field of the Invention
The invention is directed to a circuit arrangement for the recognition of impermissable phase errors in a phase locked loop wherein means are provided for generating phase signals by a phase comparison of binary data signals and clock signals and wherein a repetition rate of clock signals generated in an oscillator is modified dependent on the phase signals.
2. Description of the Prior Art
In a playback of data recorded on a recording medium, for example on a magnetic tape or on a magnetic disk, the data signals output by a transducer, for example, a magnetic head, can be distorted in various ways. The distortions can occur as a result of fluctuations in the relative speed between the recording medium and the transducer. This can occur due to noise, dust particles, inadequacies in the surface of the recording medium, or, in the case of a magnetic recording medium, due to the particular properties of the magnetic particles. In order to assure the best possible playback of the data stored by the data signals, a phase locked loop, also referred to as a PLL, is employed in order to generate lock signals which are synchronized with the played back data signals. The phase locked loop can be designed both as an analog as well as a digital circuit.
Such a phase locked loop designed as an analog circuit is shown in FIG. 1. The analog data signals AD proceed from a data source DS, for example, a magnetic head of a magnetic tape recorder means or of a magnetic disk storage, to a digitization stage DI which generates binary data signals D from the analog data signals. These data signals D are supplied to the phase locked loop PLL which generates clock signals C serving as reference clock signals. The clock signals C are generated in a voltage-controlled oscillation VCO and, just like the data signals D, are supplied to a phase comparator PC. Dependent upon whether the data signals D lead or trail the clock signals C, this generates phase signals E or L whose duration corresponds to the amount of lead or trail. An amplifier A generates an error signal ER1 from these phase signals EL and conducts it to a filter F, usually a low-pass filter, which generates a control signal ER and emits this to the voltage-controlled oscillator VCO. This modifies the frequency of the clock signals C dependent on the momentary value of the control signal ER such that a phase difference between the data signals D and the clock signals C is opposed.
In the illustration of FIG. 2, the data signals D' are ideal data signals wherein the spacings of the leading edges differ by whole-numbered factors dependent on the data to be recorded.
It can occur in a recording onto a recording medium that successive data signals D are shifted in opposite directions. This particularly occurs when the spacings of the data signals change and the data signals D are then respectively shifted toward the gap which thus arises. This event is also referred to as "bit shift" and is identified as BS in FIG. 2. However, it can also occur that, due for example to a fluctuation in the relative speed between the recording medium and the transducer, the data signals D are shifted in one direction, this then being referred to as a frequency deviation and being identified as FD in FIG. 2.
In both cases, the phase locked loop PLL has the job of eliminating the influences of these effects. Given a frequency deviation FD, there is no difficulty in modifying the frequency of the clock signals C in one direction. However, there is a risk that in the first, data-dependent shift as shown, for example, at point in time T1, the oscillator VCO is adjusted in the same way as it is adjusted given a frequency deviation FD corresponding to a trailing of the data signals D. In the following data signal D as shown, for example at point in time T2, the data signal D is leading in comparison to the clock signal C. It can thus occur that the synchronization between the data signals D and the clock signals C is lost, and thus the recorded data cannot be unambiguously re-acquired.
Given a trailing of the data signals D in comparison to the clock signals C, phase signals L are generated at points in time T1 and T3 through T5, whereas a phase signal E is generated at point in time T2 given leading data signals. The amplifier A and the filter F generate the control signal ER from the phase signals E and L, this control signal ER being supplied to the oscillator VCO in order to modify the frequency of the clock signal C to assure the best possible synchronization between the clock signals C and the data signals D.
The filter F is normally in position to compensate the data dependent bit shifts BS. However, given storages of which especially high demands are made, it can occur that the elimination of the information-dependent bit shifts is extremely difficult without disturbing the high-frequency behavior of the phase locked loop PLL.